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YAC520
HGVC1
High Grade Volume Control
s Outline
YAC520(HGVC1) is a high grade stereophonic digital volume for high end audio system. It provides wide dynamic range and low distortion as well, and can control individual channels in 256 steps with 0.5 dB per step. The use of 16 bit serial data interface allows daisy chain connection of several devices for multi channel system. Zero Crossing Detection function suppresses audible noise at quick change of the volume. YAC520 operates on a single 5 volt power supply, and it is possible to input signal of up to 7.9Vrms by using three types of connection methods. Development evaluation board, DMB-HGVC1, equipped with PC interface is available.
s Features
q Wide volume range (can be used in three ways) q Adjustment step q Gain Error q Low distortion factor q Low residual noise A: +32.0 to - 95.0dB IN1=IN2 (Input < 2.0Vrms @VDD=5V) B: +29.5 to - 97.5dB IN2=GND (Input < 2.6Vrms @VDD=5V) C: +20.0 to - 107.0dB IN1=GND (Input < 7.9Vrms @VDD=5V) adjustable in 256 steps, with 0.5dB per step 0.1dB 0.001% (input=150 mVrms, gain=+16dB) 1 Vrms (gain=- )
s Others
Process Package Power supply voltage Operating temperature Power consumption CMOS process 20 SSOP (YAC520-E) 5V 0 to +70 C 100 mW @VDD=5.0 V
YAC520 CATALOG CATALOG No.: LSI-4AC520A4 2001.12
YAC520
s Block Diagram
VREF + -
LIN2 LIN1 Vref Generator & Reset pulse Generator LOUT
256
VREF
DVSS DVDD L Zero Cross Detection AVSS AVDD R
Reset
ICN TE
Control Register
ZCEN SDATAO 16 S/P Register SDATAI CSN SCLK
256
RIN1 RIN2
ROUT
+ VREF
2
YAC520
s Pin Assignment
SCLK SDATAO DVDD DVSS AVSS AVDD ROUT VREF LOUT AVSS
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
SDATAI CSN ZCEN ICN TE RIN1 RIN2 AVSS LIN2 LIN1
Top View
3
YAC520
s Pin Functions
* Power supply pins AVDD - AVSS - DVDD - DVSS - Analog power supply (+5.0 V) Analog ground Digital power supply (+5.0 V) Digital ground
* Analog Pins LIN1 - Left Channel Analog input 1 Lch analog input pin 1 Gain setting ranges from +32 dB to - 95 dB when the signal inputted to LIN2 is inputted this pin, and gain setting ranges from +20.0 dB to - 107.0 dB when it is grounded through a capacitor. LIN2 - Left Channel Analog input 2 Lch analog input pin 2 Gain setting ranges from +32 dB to - 95 dB when the signal inputted to LIN1 is inputted this pin, and gain setting ranges from +29.5 dB to - 97.5 dB when it is grounded through a capacitor. RIN1 - Right Channel Analog input 1 Rch analog input pin 1 Gain setting ranges from +32 dB to - 95 dB when the signal inputted to RIN2 is inputted this pin, and gain setting ranges from +20.0 dB to - 107.0 dB when it is grounded through a capacitor. RIN2 - Right Channel Analog input 2 Rch analog input pin 2 Gain setting ranges from +32 dB to - 95 dB when the signal inputted to RIN1 is inputted this pin, and gain setting ranges from +29.5 dB to - 97.5 dB when it is grounded through a capacitor. LOUT - Left Channel Analog output Lch analog output pin Note this is an inverted output. ROUT - Right Channel Analog output Rch analog output pin Note this is an inverted output. VREF - Analog Reference Voltage (output) Analog reference voltage output pin Outputs 1/2VDD. Ground through a capacitor of 10 F or more to attain stabilization. * Digital Pins SDATAI - Serial Data Input Serial data input pin SDATAO - Serial Data Output Serial data putput pin Outputs Serial data when CSN is "low", or becomes high impedance state when it is "high". SCLK - Serial Clock (Input) Serial clock input pin CSN - Chip Select (Input) Chip select input pin ICN - DC Bias Initial Clear (Input) DC bias initialization pin. DC bias is set to VREF (analog reference voltage) when this is "low". To stabilize the bias voltage at power on, determine the control time in accordance with the coupling capacitor that is connected to the inputs (LIN1, LIN2, RIN1 ,RIN2). (Refer to "VREF stabilization time and DC bias initialization time" in the description of functions.) ZCEN - Zero Crossing Enable (Input) Zero crossing control pin. Making this pin "high" enables a mode where volume change is performed after detecting zero crossing. The volume change immediately after writing data when this pin is "low". TE - Test Enable (Input) Test mode control pin. Fix it to "low" or with NC when using. 4
YAC520
s Description of analog functions
* Maximum input voltage As described in the following figure, the maximum amplitude of signal that can be inputted varies according the method of the use of L(R) IN1 and 2 pins. The method A makes the maximum amplitude of the input signal approximately 2 Vrms, the method B makes it approximately 2.6 Vrms, and the method C makes it approximately 7.9 Vrms. The use of the method B or C allows to input signal exceeding the power supply voltage. Note that the gain setting range for the method B is reduced by 2.5 dB from the one for the method A, and 12 dB for the method C.
L(R) IN1 L(R) IN2 Ri(2) **** + Ri(1) Rf L(R) IN1 L(R)OUT L(R) IN2 Ri(2) **** + Ri(1) Rf L(R)OUT
VREF
VREF
MethodA: IN1=IN2 Gain range (+32 dB to -95 dB) Maximum input voltage: 2 Vrms
Rf L(R)OUT
MethodB: IN2=GND Gain range (+29.5 dB to -97.5 dB) Maximum input voltage: 2.6 Vrms
L(R) IN1 L(R) IN2
Ri(1)
Ri(2)
**** +
VREF
MethodC: IN1=GND
Gain range (+20 dB to -107 dB)
Maximum input voltage: 7.9 Vrms
* VREF (analog reference voltage) stabilization time and DC bias initialization time The time required for stabilization of VREF pin voltage after power on moment varies according to the capacitance of the capacitor connected to VREF pin. Connecting a capacitor of 10 F makes the time constant 30 ms (typ.). Note that the serial interface becomes invalid in this period, tPUP. As shown in the following figure, making ICN terminal "low" sets the DC bias forcibly with SW in the LSI. Since the time constant of L(R) IN1 and 2 pins becomes approximately 300 ms (typ.) when a capacitor of 100 F is used as the coupling capacitors (Ci1, 2), control ICN according to the capacitor that is connected.
ICN SW Ci1 Audio Source Ci2 L(R) IN1 Ri1=0.98k L(R) IN2 Ri2=2.94k + Rsw= 80 (typ) L(R)OUT Rf=29.3k
VREF
Gain setting after power on = -
5
YAC520
s Realization of system with low residual noise
- Configuration that uses HGVC1 -
HGVC1 + - + 16dB to 1 Vrms +30dB 30 Vrms 0 Vrms +16dB 1 Vrms +30dB 30 Vrms
- Conventional configuration -
Volume+PreAMP
MainAMP
Volume
PreAMP
MainAMP
General audio amplifiers are designed with the input sensitivity of approximately 150mV, and has gain of approximately 16 dB at PreAMP section, and approximately 30 dB at Power AMP section. For passive volume, they are given configuration of "Volume"-"PreAMP"-"MainAMP" as shown in the above right figure. System with very small residual noise can be made by giving HGVC1 also the function of "PreAMP" because HGVC1 has the positive side gain (max : 32 dB). Since the residual noise of HGVC1 (gain=- ) is 1 Vrms(typ.), the noise level at the speaker end becomes 30 Vrms if the noise of MainAMP is neglected. On the other hand, when conventional configuration is used, the noise at the speaker end becomes very large because the noise produced by the initial stage of PreAMP is amplified approximately by 46 dB (200 times) even if the level of noise produced by the volume section during mute is zero. To achieve the noise level at the speaker end that is equivalent to the one obtained with configuration using HGVC1, the level of the noise converted to that of input of PreAMP is required to be approximately 0.16 Vrms (-136 dBV), which is very difficult to achieve. As described above, HGVC1 provides advantage of making the residual noise very small because it has built-in amplifiers.
6
YAC520
s Description of digital functions
* Serial data interface HGVC1 is a simple three wire serial interface. SDATAI is a serial data input pin, SCLK is a serial clock pin, and CSN is a chip select pin for writing volume value. 16 bit serial data is so formatted that SDATAI is inputted in synchronous with rise edge of SCLK when CSN is "low" (MSB first). Data is latched with the rise edge of CSN, and volume values of both left channel and right channel are set into the register. Serial data is outputted from SDATAO in synchronous with fall edge of SCLK. This data allows control by using daisy chain connection or confirmation of present volume value easily. Note that the register value after power on is 0000h (muted state), and thus, the interface becomes valid after the time tPUP elapses. CSN SCLK SDATAI SDATAO
R1[7] R1[6] R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] L1[7] L1[6] L1[5] L1[4] L1[3] L1[2] L1[1] L1[0]
R0[7] R0[6] R0[5] R0[4] R0[3] R0[2] R0[1] R0[0] L0[7] L0[6] L0[5] L0[4] L0[3] L0[2] L0[1] L0[0] R1[7]
* Daisy Chaining Since HGVC1 adopts multi channel system, multiple devices can be connected with daisy chain connection. When using the LSI in multi channel system, connection of the first SDATAO pin to the second SDATAI pin, and the second SDATAO pin to the third SDATAI pin allows control of multiple HGVC1s without requiring complex addressing. Volume data is inputted into the S/P(Serial/Parallel) register of the individual HGVC1 by holding CSN "low" for 16 clocks * N (N represents the number of HGVCs in the chain). As the volume data inputted to the SDATAI of HGVC1(1) is shifted in the internal S/P register by 1 bit per SCLK clock, 16 * N clocks are required to input volume data into S/P registers of all HGVC1(1) to HGVC1(N). Note that the first 16-bit data is inputted to the S/P register of the HGVC1(N). Finally, by setting CSN "High" after 16 clocks * N period, all data in the S/P registers are written into the Control registers simultaneously to activate new volume data of all HGVC1s in the daisy chain.
Audio Source
LIN1 LIN2 RIN1 RIN2
Audio Source
LIN1 LIN2 RIN1 RIN2
Audio Source
LIN1 LIN2 RIN1 RIN2
LOUT ROUT HGVC1 (N)
LOUT
LOUT ROUT HGVC1 (1)
*** ***
ROUT
HGVC1 (2)
SDATAO CSN
SDATAI SCLK
SDATAO CSN
SDATAI SCLK
SDATAO CSN
SDATAI SCLK
Controller
CSN SCLK SDATAI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
R N [7:0] L N[7:0] R N-1[7:0]
*** ***
16(N-1)+1
R 1[7:0] L 1[7:0]
16N
7
YAC520
* Volume Setting In zero crossing mode (ZCEN=H), the volume value is changed when one zero crossing is detected after the rise of CSN. The volume value is changed also when no zero crossing is detected for 20 ms. In normal mode (ZCEN=L), zero crossing detection is not performed and volume value is changed immediately after the rise of CSN. The input codes and volumes values are related as described in the following table.
Input Code (Left/Right Channel) 11111111 11111110
* *
L(R)IN1=L(R)IN2 L(R)IN2=GND L(R)IN1=GND Gain or Attenuation (dB) Gain or Attenuation (dB) Gain or Attenuation (dB) +32.0 +31.5
* *
+29.5 +29.0
* *
+20.0 +19.5
* *
11010111
*
+12.0
*
+9.5
*
0 -9.5 -12.0 -106.5 -107.0 MUTE
* * * *
11000100
*
+2.5
*
0 -2.5 -97.0 -97.5 MUTE
* * *
10111111
* *
0 -94.5 -95.0 MUTE
* *
00000010 00000001 00000000
* MUTE
Writing 0000h into register enables mute. The time mute is enabled varies between zero crossing mode (ZCEN=H) and normal mode (ZCEN=L) as described above.
8
YAC520
s Electrical Characteristics
q Absolute maximum ratings Parameter Analog Supply Voltage Digital Supply Voltage Analog Input Voltage
@AVDD=DVDD=5V
Symbol AVDD DVDD
min. - 0.3 - 0.3 - - - - 0.3 - 50
max. 7.0 7.0 2.0 2.6 7.9 DVDD+0.3 125
Unit V V Vrms
(A: LIN1=LIN2, RIN1=RIN2) (B: LIN2=GND, RIN2=GND) (C: LIN1=GND, RIN1=GND)
VINA
Digital Input Voltage Storage Temperature Note) DVSS = AVSS = 0V q Recommended operating conditions Parameter Analog Operating Voltage Digital Operating Voltage Operating Ambient Temperature Symbol AVDD DVDD TOP
VIND Tstg
V C
min. 4.75 4.75 0
typ. 5.00 5.00 25
max. 5.25 5.25 70
Unit V V C
q Analog Characteristics (Conditions: TOP = 25C, AVDD = DVDD = 5.0V) Parameter Gain Range (A: LIN1=LIN2, RIN1=RIN2) (B: LIN2=GND, RIN2=GND) (C: LIN1=GND, RIN1=GND) Step Size Step Error Gain Matching Between Channel (1kHz) Input Resistance Input Capacitance Load Capacitance Output Impedance Signal to Noise Ratio (input=150mVrms, gain=+16dB) Total Harmonic Distortion (input=150mVrms, gain=+16dB) Residual Output Noise (, IHF-A) RI CI CL RO SN THD Vn Symbol Gain A Gain B Gain C min. - 95.0 - 97.5 - 107.0 - - - 0.5 - - - - - - - 1.5 0.5 0.1 0.1 - - - 50 100 0.001 1 - 110 - - typ. max. + 32.0 + 29.5 + 20.0 - - - 40 15 100 - - - - - - dB dB dB k pF pF dB % Vrms dB Vrms dB Unit
Inter channel Isolation (1kHz) Output Clipping Voltage (THD < 0.1%, RL = 10k)
9
YAC520
q Power Supply Parameter Power Consumption (AVDD,DVDD=5V) q Digital DC Characteristics Parameter High-Level Input voltage Low-Level Input voltage High-Level Output voltage(Io= - 0.2mA) Low-Level Output voltage(Io=2mA) Input Leakage Current q Digital AC Characteristics Parameter Serial Clock Serial Clock Pulse Width High Serial Clock Pulse Width Low SDATAI Set Up Time SDATAI Hold Time CSN Valid to SCLK Rising SCLK Falling to CSN High CSN low to Output Active SCLK Falling to Data Valid CSN High to SDATAO Inactive Power-up to SPI Operation (CVREF=10F) (CL=20 pF) (CL=20 pF) Symbol SCLK min. - 80 80 20 20 30 35 - - - - typ. - - - - - - - - - - 30 max. 6.25 - - - - - - 35 60 100 50 Unit MHz ns ns ns ns ns ns ns ns ns ms Symbol VIH VIL VOH VOL ILI min.
0.7xVDD
Symbol PD
min. -
typ. 100
max. -
Unit mW
typ. - - - - -
max. -
0.3xVDD
Unit V V V V A
- VDD-1 - -
- 0.4 10
tPH tPL tSDVS tSDH tCSVS tLTH tCSH tSSD tCSDH tPUP
CSN tCSVS SCLK tSDH SDATAI tCSDH SDATAO tCSH MSB tSSD tSDVS tLTH
Serial Port Timing Diagram
10
YAC520
s Example of System Configuration (1)
A type (+32.0 to - 95.0dB) LIN1=LIN2 RIN1=RIN2
100F + 11 LIN1 12 LIN2 13 AVSS 14 RIN2 + 100F 15 RIN1 16 TE 17 ICN 18 ZCEN AVSS 10 LOUT 9 VREF 8 ROUT 7 AVDD 6 AVSS 5 DVSS 4 DVDD 3 SDATAO 2 SCLK 1 47k 0.1F 47F HGVC1(SDATAI) or Controller 0.1F 47F 4.7 +5v 10F 10F 220 10F 220 Audio Output Lch Audio Output Rch
Audio Source
Digital Controller
19 CSN 20 SDATAI
SDATAO is high impedance state when CSN is high.
B type (+29.5 to - 97.5dB) LIN2=GND RIN2=GND
+ 100F 33F 11 LIN1 12 LIN2 13 AVSS 33F + 100F 14 RIN2 15 RIN1 16 TE 17 ICN 18 ZCEN AVSS 10 LOUT 9 VREF 8 ROUT 7 AVDD 6 AVSS 5 DVSS 4 DVDD 3 SDATAO 2 SCLK 1 47k 0.1F 47F HGVC1(SDATAI) or Controller 0.1F 47F 4.7 10F 10F 220 +5v
10F
220
Audio Source
Audio Output Lch Audio Output Rch
Digital Controller
19 CSN 20 SDATAI
SDATAO is high impedance state when CSN is high.
C type (+20.0 to - 107.0dB) LIN1=GND RIN1=GND
100F + 33F 11 LIN1 12 LIN2 13 AVSS 100F 14 RIN2 15 RIN1 16 TE 17 ICN 18 ZCEN AVSS 10 LOUT 9 VREF 8 ROUT 7 AVDD 6 AVSS 5 DVSS 4 DVDD 3 SDATAO 2 SCLK 1 47k 0.1F 47F HGVC1(SDATAI) or Controller 0.1F 47F 4.7 +5v 10F 10F 220 10F 220 Audio Output Lch Audio Output Rch
Audio Source
+
33F
Digital Controller
19 CSN 20 SDATAI
SDATAO is high impedance state when CSN is high.
11
s Example of System Configuration (2)
12
L/R,C,SL/SR,SW
COAXIAL DIGITAL
DSP BLOCK +32dB~-95dB / 0.5dB step +5V +- 12V
+
BassOut:Main Center:None
OPTICAL DIGITAL
+- 12V
+ L/R
Tone Control/ Blance/ Bass Extension
HP MUTE
HEADPHONES
INPUT SELECTOR HGVC1 2CH
PA
MAIN A
+--+
MAIN B
+--+
MICRO CONTROLLER
ZONE2 OUT L/R
INPUT C/SW + HGVC1 2CH
Front:None
REC OUT/ ZONE2 SELECTOR
CENTER
PA +-
MUTE -
SUB WOOFER
+-
CD L/R TUNER L/R MD L/R TAPE L/R DVD L/R LD L/R D-TV L/R SAT L/R VCR L/R V-AUX L/R
SL/SR +
SURROUND
PA PA : POWER AMP +--+
INHIBIT
HGVC1 2CH
REC OUT
L/R
MD L/R TAPE L/R VCR L/R
C
RELAY DRIVER MUTE DRIVER
6ch INPUT
SL/SR
SW
ZONE2 VOLUME
YAC520
6 channels system
YAC520
s Example of PCB Layout
Digital Logic Digital Ground Plane
SDATAI
SDATAO
Analog Circuit
47F 0.1F DVDD +5V 4.7 AVDD 47F 0.1F 10F 4.7
47F 0.1F
47F 0.1F 10F
Analog Ground Plane
To achieve the maximum performance of this device, it is necessary to take special care for the power supply and the method of grounding. (The above figure shows an example of the layout on the PCB that assumes the daisy chain connection of two HGVC1s.) Connect a regulated low noise 5 V power supply to AVDD, and de-couple with DVDD through a resistor for the purpose of avoiding mixing of noise that is generated in the serial interface. (Refer to s Example of System Configuration) At this time, the decoupling capacitor should be located as close as possible to HGVC1. The analog domain and digital domain should be grounded separately, and HGVC1 should be located in the analog domain side, so that a pattern layout with minimized impedance to AVSS and DVSS pins can be achieved. The analog ground and digital ground should be given sufficiently wide areas respectively so that the radiation of the noise can be suppressed effectively. Control signals such as serial interface should be placed collectively in the area nearer to the digital ground
plane (upper side), and analog signals and digital signals should be arranged without crossing each other and without running side by side to prevent their interference.
13
YAC520
s External Dimensions of Package
14
YAC520
MEMO
15
YAC520
IMPORTANT NOTICE
1. Yamaha reserves the right to make changes to its Products and to this document without notice. The information contained in this document has been carefully checked and is believed to be reliable. However, Yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or to keep current the information contained in this document. 2. These Yamaha Products are designed only for commercial and normal industrial applications, and are not suitable for other uses, such as medical life support equipment, nuclear facilities, critical care equipment or any other application the failure of which could lead to death, personal injury or environmental or property damage. Use of the Products in any such application is at the customer's sole risk and expense. 3. YAMAHA ASSUMES NO LIABILITY FOR INCIDENTAL, CONSEQUENTIAL, OR SPECIAL DAMAGES OR INJURY THAT MAY RESULT FROM MISAPPLICATION OR IMPROPER USE OR OPERATION OF THE PRODUCTS. 4. YAMAHA MAKES NO WARRANTY OR REPRESENTATION THAT THE PRODUCTS ARE SUBJECT TO INTELLECTUAL PROPERTY LICENSE FROM YAMAHA OR ANY THIRD PARTY, AND YAMAHA MAKES NO WARRANTY OR REPRESENTATION OF NON-INFRANGIMENT WITH RESPECT TO THE PRODUCTS. YAMAHA SPECIALLY EXCLUDES ANY LIABILITY TO THE CUSTOMER OR ANY THIRD PARTY ARISING FROM OR RELATED TO THE PRODUCTS' INFRINGEMENT OF ANY THIRD PARTY'S INTELLECTUAL PROPERTY RIGHTS, INCLUDING THE PATENT, COPYRIGHT, TRADEMARK OR TRADE SECRET RIGHTS OF ANY THIRD PARTY. 5. EXAMPLES OF USE DESCRIBED HEREIN ARE MERELY TO INDICATE THE CHARACTERISTICS AND PERFORMANCE OF YAMAHA PRODUCTS. YAMAHA ASSUMES NO RESPONSIBILITY FOR ANY INTELLECTUAL PROPERTY CLAIMS OR OTHER PROBLEMS THAT MAY RESULT FROM APPLICATIONS BASED ON THE EXAMPLES DESCRIBED HEREIN. YAMAHA MAKES NO WARRANTY WITH RESPECT TO THE PRODUCTS, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR USE AND TITLE.
Notice
The specification given here are provisional and subject to change without prior notice. Please confirm the latest documentation before using this product.

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